In recent years, the freefall of processor cycle times to levels well below access times of most dynamic random access memories has generated extensive research, the result of which has been formation of synchronous memory devices. Virtually all currently available semiconductor dynamic random access memory (DRAM) and many static random access memory (SRAM) devices use asynchronous clocking systems in that the clocking signals necessary to perform memory access functions are not synchronized to the associated system processor. Although memories are accessed by signals sent by the processor, the exact time interval between the time a request is sent to a memory and the time a response is received is dependent on the particular internal features of the memory. Thus, it is necessary for system designers to allow for the "worst case" response time between requests for information and the anticipated time the information will be available, which necessarily wastes time in the handling of many memory functions.
Semiconductor processing technology has enabled logic components such as microprocessors to operate at, for example, 66-100 megahertz (Mhz) clock rates. Until recently, memory system clock rates have not kept pace because of the nature of operations performed. In order to meet these higher speed processors, synchronous dynamic random access memories (SDRAMs), operable with clock rates of up to 66-100 Mhz., have been designed. SDRAMs are responsive to a high frequency clock signal generated by the processor, or at least in synchronization with the processor, which renders all internal activity within the memory "synchronous" with other devices responsive to the same clock signal(s). In the synchronous approach, all SDRAM inputs are sampled at the positive edge of the input clock, and all SDRAM outputs are valid on subsequent positive edges. This technique permits input/output transactions to take place on every clock cycle. SDRAMs can simplify both the overall system design and the memory-management subsystem, because the main memory no longer has to be asynchronous to the system clock.
Packaging of multiple SDRAM devices is one particular problem to be addressed with the emergence of this new technology. In general, the synchronous memory chip contains a standard DRAM array core plus many of the same features included in a standard DRAM. However, in addition to row and column decoders, and a refresh counter, such devices incorporate special latency and burst-length registers, a data-input register, and programming and timing registers. These new SDRAM registers also require that system designers accommodate a few new signal lines, for example, clock and clock enable lines, as well as data input/output mask control lines.
Single in-line memory modules (SIMMs) are compact circuit boards designed to accommodate surface mounted memory chips, such as DRAMs. SIMMs were developed to provide compact and easy-to-manage modular memory components for user installation in computer systems designed to accept such SIMMs. A SIMM generally is easily inserted into a connector within the computer system, the SIMM thereby deriving all necessary power, ground, and logic signals therefrom. Recently, dual in-line memory modules (DIMMs) have begun to replace SIMMs as the compact circuit boards of preference. A DIMM essentially comprises a SIMM wherein memory chips are surface mounted to opposite sides of the circuit board, and the connector tabs are unique on each side. The industry has standardized a 168 pin DIMM design for dynamic random access memories. The 168 pin 8 byte DIMM family has been developed as an optimized low cost main memory solution for 4 and 8 byte processor applications. The family includes 64 bit non-parity, 72 bit parity, 72 bit ECC, and 80 bit ECC memory organizations. A significant portion of the connectors, motherboards, etc., presently marketed for DIMM packages are configured to accommodate this 168 pin configuration for main memory.
There is currently activity in the semiconductor packaging industry to design a low cost DIMM to fully utilize the high speed synchronous dynamic random access memories. The industry is currently discussing the implementation of a new 200 pin DIMM to accommodate the extra signals required to drive synchronous DRAMs. However, this new design will also require reconfiguration of the connector, motherboard, etc., into which the 200 pin DIMM would be inserted, along with occupying greater area. Because of the wide acceptance of the 168 pin DIMM outline, the reduced space required thereof and the benefits of being able to design a common motherboard for both DRAM and SDRAM applications, implementation of SDRAMs in a 168 pin DIMM is believed clearly preferential.